
nv21-rgb:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400448 <_init>:
  400448:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40044c:	910003fd 	mov	x29, sp
  400450:	9400002a 	bl	4004f8 <call_weak_fn>
  400454:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400458:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400460 <.plt>:
  400460:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400464:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf660>
  400468:	f947fe11 	ldr	x17, [x16, #4088]
  40046c:	913fe210 	add	x16, x16, #0xff8
  400470:	d61f0220 	br	x17
  400474:	d503201f 	nop
  400478:	d503201f 	nop
  40047c:	d503201f 	nop

0000000000400480 <__libc_start_main@plt>:
  400480:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400484:	f9400211 	ldr	x17, [x16]
  400488:	91000210 	add	x16, x16, #0x0
  40048c:	d61f0220 	br	x17

0000000000400490 <__gmon_start__@plt>:
  400490:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400494:	f9400611 	ldr	x17, [x16, #8]
  400498:	91002210 	add	x16, x16, #0x8
  40049c:	d61f0220 	br	x17

00000000004004a0 <abort@plt>:
  4004a0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004a4:	f9400a11 	ldr	x17, [x16, #16]
  4004a8:	91004210 	add	x16, x16, #0x10
  4004ac:	d61f0220 	br	x17

Disassembly of section .text:

00000000004004b0 <_start>:
  4004b0:	d280001d 	mov	x29, #0x0                   	// #0
  4004b4:	d280001e 	mov	x30, #0x0                   	// #0
  4004b8:	aa0003e5 	mov	x5, x0
  4004bc:	f94003e1 	ldr	x1, [sp]
  4004c0:	910023e2 	add	x2, sp, #0x8
  4004c4:	910003e6 	mov	x6, sp
  4004c8:	580000c0 	ldr	x0, 4004e0 <_start+0x30>
  4004cc:	580000e3 	ldr	x3, 4004e8 <_start+0x38>
  4004d0:	58000104 	ldr	x4, 4004f0 <_start+0x40>
  4004d4:	97ffffeb 	bl	400480 <__libc_start_main@plt>
  4004d8:	97fffff2 	bl	4004a0 <abort@plt>
  4004dc:	00000000 	.inst	0x00000000 ; undefined
  4004e0:	004008b8 	.word	0x004008b8
  4004e4:	00000000 	.word	0x00000000
  4004e8:	004008f0 	.word	0x004008f0
  4004ec:	00000000 	.word	0x00000000
  4004f0:	00400970 	.word	0x00400970
  4004f4:	00000000 	.word	0x00000000

00000000004004f8 <call_weak_fn>:
  4004f8:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf660>
  4004fc:	f947f000 	ldr	x0, [x0, #4064]
  400500:	b4000040 	cbz	x0, 400508 <call_weak_fn+0x10>
  400504:	17ffffe3 	b	400490 <__gmon_start__@plt>
  400508:	d65f03c0 	ret
  40050c:	00000000 	.inst	0x00000000 ; undefined

0000000000400510 <deregister_tm_clones>:
  400510:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400514:	9100a000 	add	x0, x0, #0x28
  400518:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40051c:	9100a021 	add	x1, x1, #0x28
  400520:	eb00003f 	cmp	x1, x0
  400524:	540000a0 	b.eq	400538 <deregister_tm_clones+0x28>  // b.none
  400528:	90000001 	adrp	x1, 400000 <_init-0x448>
  40052c:	f944c821 	ldr	x1, [x1, #2448]
  400530:	b4000041 	cbz	x1, 400538 <deregister_tm_clones+0x28>
  400534:	d61f0020 	br	x1
  400538:	d65f03c0 	ret
  40053c:	d503201f 	nop

0000000000400540 <register_tm_clones>:
  400540:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400544:	9100a000 	add	x0, x0, #0x28
  400548:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40054c:	9100a021 	add	x1, x1, #0x28
  400550:	cb000021 	sub	x1, x1, x0
  400554:	9343fc21 	asr	x1, x1, #3
  400558:	8b41fc21 	add	x1, x1, x1, lsr #63
  40055c:	9341fc21 	asr	x1, x1, #1
  400560:	b40000a1 	cbz	x1, 400574 <register_tm_clones+0x34>
  400564:	90000002 	adrp	x2, 400000 <_init-0x448>
  400568:	f944cc42 	ldr	x2, [x2, #2456]
  40056c:	b4000042 	cbz	x2, 400574 <register_tm_clones+0x34>
  400570:	d61f0040 	br	x2
  400574:	d65f03c0 	ret

0000000000400578 <__do_global_dtors_aux>:
  400578:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40057c:	910003fd 	mov	x29, sp
  400580:	f9000bf3 	str	x19, [sp, #16]
  400584:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  400588:	3940a260 	ldrb	w0, [x19, #40]
  40058c:	35000080 	cbnz	w0, 40059c <__do_global_dtors_aux+0x24>
  400590:	97ffffe0 	bl	400510 <deregister_tm_clones>
  400594:	52800020 	mov	w0, #0x1                   	// #1
  400598:	3900a260 	strb	w0, [x19, #40]
  40059c:	f9400bf3 	ldr	x19, [sp, #16]
  4005a0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4005a4:	d65f03c0 	ret

00000000004005a8 <frame_dummy>:
  4005a8:	17ffffe6 	b	400540 <register_tm_clones>

00000000004005ac <NV21_T_RGB>:
  4005ac:	d10143ff 	sub	sp, sp, #0x50
  4005b0:	b9001fe0 	str	w0, [sp, #28]
  4005b4:	b9001be1 	str	w1, [sp, #24]
  4005b8:	f9000be2 	str	x2, [sp, #16]
  4005bc:	f90007e3 	str	x3, [sp, #8]
  4005c0:	b9401fe1 	ldr	w1, [sp, #28]
  4005c4:	b9401be0 	ldr	w0, [sp, #24]
  4005c8:	1b007c20 	mul	w0, w1, w0
  4005cc:	b90037e0 	str	w0, [sp, #52]
  4005d0:	b90033ff 	str	wzr, [sp, #48]
  4005d4:	b90047ff 	str	wzr, [sp, #68]
  4005d8:	b9002fff 	str	wzr, [sp, #44]
  4005dc:	b9004fff 	str	wzr, [sp, #76]
  4005e0:	140000af 	b	40089c <NV21_T_RGB+0x2f0>
  4005e4:	b9004bff 	str	wzr, [sp, #72]
  4005e8:	140000a6 	b	400880 <NV21_T_RGB+0x2d4>
  4005ec:	b9404fe0 	ldr	w0, [sp, #76]
  4005f0:	53017c01 	lsr	w1, w0, #1
  4005f4:	b9401fe0 	ldr	w0, [sp, #28]
  4005f8:	1b007c21 	mul	w1, w1, w0
  4005fc:	b9404be0 	ldr	w0, [sp, #72]
  400600:	0b000021 	add	w1, w1, w0
  400604:	b9404be0 	ldr	w0, [sp, #72]
  400608:	12000000 	and	w0, w0, #0x1
  40060c:	4b000020 	sub	w0, w1, w0
  400610:	b9002fe0 	str	w0, [sp, #44]
  400614:	b94047e0 	ldr	w0, [sp, #68]
  400618:	f9400be1 	ldr	x1, [sp, #16]
  40061c:	8b000020 	add	x0, x1, x0
  400620:	39400000 	ldrb	w0, [x0]
  400624:	3900afe0 	strb	w0, [sp, #43]
  400628:	b94037e1 	ldr	w1, [sp, #52]
  40062c:	b9402fe0 	ldr	w0, [sp, #44]
  400630:	0b000020 	add	w0, w1, w0
  400634:	93407c00 	sxtw	x0, w0
  400638:	f9400be1 	ldr	x1, [sp, #16]
  40063c:	8b000020 	add	x0, x1, x0
  400640:	39400000 	ldrb	w0, [x0]
  400644:	3900abe0 	strb	w0, [sp, #42]
  400648:	b94037e1 	ldr	w1, [sp, #52]
  40064c:	b9402fe0 	ldr	w0, [sp, #44]
  400650:	0b000020 	add	w0, w1, w0
  400654:	93407c00 	sxtw	x0, w0
  400658:	91000400 	add	x0, x0, #0x1
  40065c:	f9400be1 	ldr	x1, [sp, #16]
  400660:	8b000020 	add	x0, x1, x0
  400664:	39400000 	ldrb	w0, [x0]
  400668:	3900a7e0 	strb	w0, [sp, #41]
  40066c:	3940afe1 	ldrb	w1, [sp, #43]
  400670:	3940a7e0 	ldrb	w0, [sp, #41]
  400674:	51020002 	sub	w2, w0, #0x80
  400678:	52801180 	mov	w0, #0x8c                  	// #140
  40067c:	1b007c40 	mul	w0, w2, w0
  400680:	5290a3e2 	mov	w2, #0x851f                	// #34079
  400684:	72aa3d62 	movk	w2, #0x51eb, lsl #16
  400688:	9b227c02 	smull	x2, w0, w2
  40068c:	d360fc42 	lsr	x2, x2, #32
  400690:	13057c42 	asr	w2, w2, #5
  400694:	131f7c00 	asr	w0, w0, #31
  400698:	4b000040 	sub	w0, w2, w0
  40069c:	0b000020 	add	w0, w1, w0
  4006a0:	b90043e0 	str	w0, [sp, #64]
  4006a4:	3940afe1 	ldrb	w1, [sp, #43]
  4006a8:	3940abe0 	ldrb	w0, [sp, #42]
  4006ac:	51020002 	sub	w2, w0, #0x80
  4006b0:	12800420 	mov	w0, #0xffffffde            	// #-34
  4006b4:	1b007c40 	mul	w0, w2, w0
  4006b8:	5290a3e2 	mov	w2, #0x851f                	// #34079
  4006bc:	72aa3d62 	movk	w2, #0x51eb, lsl #16
  4006c0:	9b227c02 	smull	x2, w0, w2
  4006c4:	d360fc42 	lsr	x2, x2, #32
  4006c8:	13057c42 	asr	w2, w2, #5
  4006cc:	131f7c00 	asr	w0, w0, #31
  4006d0:	4b000040 	sub	w0, w2, w0
  4006d4:	0b000021 	add	w1, w1, w0
  4006d8:	3940a7e0 	ldrb	w0, [sp, #41]
  4006dc:	51020002 	sub	w2, w0, #0x80
  4006e0:	128008c0 	mov	w0, #0xffffffb9            	// #-71
  4006e4:	1b007c40 	mul	w0, w2, w0
  4006e8:	5290a3e2 	mov	w2, #0x851f                	// #34079
  4006ec:	72aa3d62 	movk	w2, #0x51eb, lsl #16
  4006f0:	9b227c02 	smull	x2, w0, w2
  4006f4:	d360fc42 	lsr	x2, x2, #32
  4006f8:	13057c42 	asr	w2, w2, #5
  4006fc:	131f7c00 	asr	w0, w0, #31
  400700:	4b000040 	sub	w0, w2, w0
  400704:	0b000020 	add	w0, w1, w0
  400708:	b9003fe0 	str	w0, [sp, #60]
  40070c:	3940afe1 	ldrb	w1, [sp, #43]
  400710:	3940abe0 	ldrb	w0, [sp, #42]
  400714:	51020002 	sub	w2, w0, #0x80
  400718:	52801620 	mov	w0, #0xb1                  	// #177
  40071c:	1b007c40 	mul	w0, w2, w0
  400720:	5290a3e2 	mov	w2, #0x851f                	// #34079
  400724:	72aa3d62 	movk	w2, #0x51eb, lsl #16
  400728:	9b227c02 	smull	x2, w0, w2
  40072c:	d360fc42 	lsr	x2, x2, #32
  400730:	13057c42 	asr	w2, w2, #5
  400734:	131f7c00 	asr	w0, w0, #31
  400738:	4b000040 	sub	w0, w2, w0
  40073c:	0b000020 	add	w0, w1, w0
  400740:	b9003be0 	str	w0, [sp, #56]
  400744:	b94043e0 	ldr	w0, [sp, #64]
  400748:	7103fc1f 	cmp	w0, #0xff
  40074c:	5400006d 	b.le	400758 <NV21_T_RGB+0x1ac>
  400750:	52801fe0 	mov	w0, #0xff                  	// #255
  400754:	b90043e0 	str	w0, [sp, #64]
  400758:	b9403fe0 	ldr	w0, [sp, #60]
  40075c:	7103fc1f 	cmp	w0, #0xff
  400760:	5400006d 	b.le	40076c <NV21_T_RGB+0x1c0>
  400764:	52801fe0 	mov	w0, #0xff                  	// #255
  400768:	b9003fe0 	str	w0, [sp, #60]
  40076c:	b9403be0 	ldr	w0, [sp, #56]
  400770:	7103fc1f 	cmp	w0, #0xff
  400774:	5400006d 	b.le	400780 <NV21_T_RGB+0x1d4>
  400778:	52801fe0 	mov	w0, #0xff                  	// #255
  40077c:	b9003be0 	str	w0, [sp, #56]
  400780:	b94043e0 	ldr	w0, [sp, #64]
  400784:	7100001f 	cmp	w0, #0x0
  400788:	5400004a 	b.ge	400790 <NV21_T_RGB+0x1e4>  // b.tcont
  40078c:	b90043ff 	str	wzr, [sp, #64]
  400790:	b9403fe0 	ldr	w0, [sp, #60]
  400794:	7100001f 	cmp	w0, #0x0
  400798:	5400004a 	b.ge	4007a0 <NV21_T_RGB+0x1f4>  // b.tcont
  40079c:	b9003fff 	str	wzr, [sp, #60]
  4007a0:	b9403be0 	ldr	w0, [sp, #56]
  4007a4:	7100001f 	cmp	w0, #0x0
  4007a8:	5400004a 	b.ge	4007b0 <NV21_T_RGB+0x204>  // b.tcont
  4007ac:	b9003bff 	str	wzr, [sp, #56]
  4007b0:	b94047e0 	ldr	w0, [sp, #68]
  4007b4:	b9401fe1 	ldr	w1, [sp, #28]
  4007b8:	1ac10802 	udiv	w2, w0, w1
  4007bc:	b9401fe1 	ldr	w1, [sp, #28]
  4007c0:	1b017c41 	mul	w1, w2, w1
  4007c4:	4b010001 	sub	w1, w0, w1
  4007c8:	b9401be2 	ldr	w2, [sp, #24]
  4007cc:	b9404fe0 	ldr	w0, [sp, #76]
  4007d0:	4b000040 	sub	w0, w2, w0
  4007d4:	51000402 	sub	w2, w0, #0x1
  4007d8:	b9401fe0 	ldr	w0, [sp, #28]
  4007dc:	1b007c40 	mul	w0, w2, w0
  4007e0:	0b000020 	add	w0, w1, w0
  4007e4:	b90033e0 	str	w0, [sp, #48]
  4007e8:	b94033e1 	ldr	w1, [sp, #48]
  4007ec:	2a0103e0 	mov	w0, w1
  4007f0:	531f7800 	lsl	w0, w0, #1
  4007f4:	0b010000 	add	w0, w0, w1
  4007f8:	2a0003e0 	mov	w0, w0
  4007fc:	f94007e1 	ldr	x1, [sp, #8]
  400800:	8b000020 	add	x0, x1, x0
  400804:	b9403be1 	ldr	w1, [sp, #56]
  400808:	12001c21 	and	w1, w1, #0xff
  40080c:	39000001 	strb	w1, [x0]
  400810:	b94033e1 	ldr	w1, [sp, #48]
  400814:	2a0103e0 	mov	w0, w1
  400818:	531f7800 	lsl	w0, w0, #1
  40081c:	0b010000 	add	w0, w0, w1
  400820:	11000400 	add	w0, w0, #0x1
  400824:	2a0003e0 	mov	w0, w0
  400828:	f94007e1 	ldr	x1, [sp, #8]
  40082c:	8b000020 	add	x0, x1, x0
  400830:	b9403fe1 	ldr	w1, [sp, #60]
  400834:	12001c21 	and	w1, w1, #0xff
  400838:	39000001 	strb	w1, [x0]
  40083c:	b94033e1 	ldr	w1, [sp, #48]
  400840:	2a0103e0 	mov	w0, w1
  400844:	531f7800 	lsl	w0, w0, #1
  400848:	0b010000 	add	w0, w0, w1
  40084c:	11000800 	add	w0, w0, #0x2
  400850:	2a0003e0 	mov	w0, w0
  400854:	f94007e1 	ldr	x1, [sp, #8]
  400858:	8b000020 	add	x0, x1, x0
  40085c:	b94043e1 	ldr	w1, [sp, #64]
  400860:	12001c21 	and	w1, w1, #0xff
  400864:	39000001 	strb	w1, [x0]
  400868:	b94047e0 	ldr	w0, [sp, #68]
  40086c:	11000400 	add	w0, w0, #0x1
  400870:	b90047e0 	str	w0, [sp, #68]
  400874:	b9404be0 	ldr	w0, [sp, #72]
  400878:	11000400 	add	w0, w0, #0x1
  40087c:	b9004be0 	str	w0, [sp, #72]
  400880:	b9404be1 	ldr	w1, [sp, #72]
  400884:	b9401fe0 	ldr	w0, [sp, #28]
  400888:	6b00003f 	cmp	w1, w0
  40088c:	54ffeb03 	b.cc	4005ec <NV21_T_RGB+0x40>  // b.lo, b.ul, b.last
  400890:	b9404fe0 	ldr	w0, [sp, #76]
  400894:	11000400 	add	w0, w0, #0x1
  400898:	b9004fe0 	str	w0, [sp, #76]
  40089c:	b9404fe1 	ldr	w1, [sp, #76]
  4008a0:	b9401be0 	ldr	w0, [sp, #24]
  4008a4:	6b00003f 	cmp	w1, w0
  4008a8:	54ffe9e3 	b.cc	4005e4 <NV21_T_RGB+0x38>  // b.lo, b.ul, b.last
  4008ac:	d503201f 	nop
  4008b0:	910143ff 	add	sp, sp, #0x50
  4008b4:	d65f03c0 	ret

00000000004008b8 <main>:
  4008b8:	d12203ff 	sub	sp, sp, #0x880
  4008bc:	a9007bfd 	stp	x29, x30, [sp]
  4008c0:	910003fd 	mov	x29, sp
  4008c4:	910043a1 	add	x1, x29, #0x10
  4008c8:	911123a0 	add	x0, x29, #0x448
  4008cc:	aa0103e3 	mov	x3, x1
  4008d0:	aa0003e2 	mov	x2, x0
  4008d4:	52805f01 	mov	w1, #0x2f8                 	// #760
  4008d8:	52808700 	mov	w0, #0x438                 	// #1080
  4008dc:	97ffff34 	bl	4005ac <NV21_T_RGB>
  4008e0:	52800000 	mov	w0, #0x0                   	// #0
  4008e4:	a9407bfd 	ldp	x29, x30, [sp]
  4008e8:	912203ff 	add	sp, sp, #0x880
  4008ec:	d65f03c0 	ret

00000000004008f0 <__libc_csu_init>:
  4008f0:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4008f4:	910003fd 	mov	x29, sp
  4008f8:	a901d7f4 	stp	x20, x21, [sp, #24]
  4008fc:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf660>
  400900:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf660>
  400904:	91374294 	add	x20, x20, #0xdd0
  400908:	913722b5 	add	x21, x21, #0xdc8
  40090c:	a902dff6 	stp	x22, x23, [sp, #40]
  400910:	cb150294 	sub	x20, x20, x21
  400914:	f9001ff8 	str	x24, [sp, #56]
  400918:	2a0003f6 	mov	w22, w0
  40091c:	aa0103f7 	mov	x23, x1
  400920:	9343fe94 	asr	x20, x20, #3
  400924:	aa0203f8 	mov	x24, x2
  400928:	97fffec8 	bl	400448 <_init>
  40092c:	b4000194 	cbz	x20, 40095c <__libc_csu_init+0x6c>
  400930:	f9000bb3 	str	x19, [x29, #16]
  400934:	d2800013 	mov	x19, #0x0                   	// #0
  400938:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  40093c:	aa1803e2 	mov	x2, x24
  400940:	aa1703e1 	mov	x1, x23
  400944:	2a1603e0 	mov	w0, w22
  400948:	91000673 	add	x19, x19, #0x1
  40094c:	d63f0060 	blr	x3
  400950:	eb13029f 	cmp	x20, x19
  400954:	54ffff21 	b.ne	400938 <__libc_csu_init+0x48>  // b.any
  400958:	f9400bb3 	ldr	x19, [x29, #16]
  40095c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400960:	a942dff6 	ldp	x22, x23, [sp, #40]
  400964:	f9401ff8 	ldr	x24, [sp, #56]
  400968:	a8c47bfd 	ldp	x29, x30, [sp], #64
  40096c:	d65f03c0 	ret

0000000000400970 <__libc_csu_fini>:
  400970:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400974 <_fini>:
  400974:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400978:	910003fd 	mov	x29, sp
  40097c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400980:	d65f03c0 	ret
